27.6.5 Interrupt Flag Status and Clear
Note: Subsequent to an interrupt flag being cleared, the flag must be read back to
verify the clear before exiting the ISR. Failure to do this can result in duplicate
interrupts.
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | INTFLAG |
Offset: | 0x0006 |
Reset: | 0x00 |
Property: | – |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SLEEPRDY | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit 0 – SLEEPRDY Sleep Mode Entry Ready
Note: Writing a ‘1’ to this bit will clear the flag and the interrupt.
Value | Description |
---|---|
0 | Device is not ready to enter Backup Sleep Mode. |
1 | Device is ready to enter Backup Sleep Mode. |