27.6.4 Interrupt Enable Set
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | INTENSET |
Offset: | 0x0005 |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SLEEPRDY | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit 0 – SLEEPRDY Backup Sleep Mode Entry Ready Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will enable the SLEEPRDY interrupt.
Note: Reading this bit returns whether this interrupt is enabled (1 =
enabled).