24.9.14 Tamper Control

Table 24-50. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: TAMPCTRL
Offset: 0x60
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
 DEBNC7DEBNC6DEBNC5DEBNC4DEBNC3DEBNC2DEBNC1DEBNC0 
Access  
Reset 00000000 
Bit 2322212019181716 
 TAMLVL7TAMLVL6TAMLVL5TAMLVL4TAMLVL3TAMLVL2TAMLVL1TAMLVL0 
Access  
Reset 00000000 
Bit 15141312111098 
 IN7ACT[1:0]IN6ACT[1:0]IN5ACT[1:0]IN4ACT[1:0] 
Access  
Reset 00000000 
Bit 76543210 
 IN3ACT[1:0]IN2ACT[1:0]IN1ACT[1:0]IN0ACT[1:0] 
Access  
Reset 00000000 

Bits 24, 25, 26, 27, 28, 29, 30, 31 – DEBNCn Debounce Enable of Tamper Input INn [n=0..7]

Note: Debounce feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL).
ValueDescription
0 Debouncing is disabled for Tamper input INn
1 Debouncing is enabled for Tamper input INn

Bits 16, 17, 18, 19, 20, 21, 22, 23 – TAMLVLn Tamper Level Select of Tamper Input INn [n=0..7]

Note: Tamper Level feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL).
ValueDescription
0 A falling edge condition will be detected on Tamper input INn.
1 A rising edge condition will be detected on Tamper input INn.

Bits 0:1, 2:3, 4:5, 6:7, 8:9, 10:11, 12:13, 14:15 – INnACT Tamper Channel n Action [n=0..7]

These bits determine the action taken by Tamper Channel n.
ValueNameDescription
0x0 OFF Off (Disabled)
0x1 WAKE Wake and set Tamper flag
0x2 CAPTURE Capture timestamp and set Tamper flag
0x3 ACTL Compare RTC signal routed between INn and OUTn pins. When a mismatch occurs, capture timestamp and set Tamper flag