24.9.8 Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCBUSY |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| GP3 | GP2 | GP1 | GP0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CLOCKSYNC | MASK1 | MASK0 | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ALARM1 | ALARM0 | CLOCK | FREQCORR | ENABLE | SWRST | ||||
| Access | R/W | R/W | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19 – GPn General Purpose n Synchronization Busy Status [n = 3..0]
| Value | Description |
|---|---|
| 0 | Write synchronization for GPn register is complete. |
| 1 | Write synchronization for GPn register is ongoing. |
Bit 15 – CLOCKSYNC Clock Read Sync Enable Synchronization Busy Status
| Value | Description |
|---|---|
| 0 | Write synchronization for CTRLA.CLOCKSYNC bit is complete. |
| 1 | Write synchronization for CTRLA.CLOCKSYNC bit is ongoing. |
Bits 11, 12 – MASKn Mask n Synchronization Busy Status [n=1..0]
| Value | Description |
|---|---|
| 0 | Write synchronization for MASKn register is complete. |
| 1 | Write synchronization for MASKn register is ongoing. |
Bits 5, 6 – ALARMn Alarm n Synchronization Busy Status [n=1..0]
| Value | Description |
|---|---|
| 0 | Write synchronization for ALARMn register is complete. |
| 1 | Write synchronization for ALARMn register is ongoing. |
Bit 3 – CLOCK Clock Register Synchronization Busy Status
| Value | Description |
|---|---|
| 0 | Read/write synchronization for CLOCK register is complete. |
| 1 | Read/write synchronization for CLOCK register is ongoing. |
Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status
| Value | Description |
|---|---|
| 0 | Write synchronization for FREQCORR register is complete. |
| 1 | Write synchronization for FREQCORR register is ongoing. |
Bit 1 – ENABLE Enable Synchronization Busy Status
| Value | Description |
|---|---|
| 0 | Write synchronization for CTRLA.ENABLE bit is complete. |
| 1 | Write synchronization for CTRLA.ENABLE bit is ongoing. |
Bit 0 – SWRST Software Reset Synchronization Busy Status
| Value | Description |
|---|---|
| 0 | Write synchronization for CTRLA.SWRST bit is complete. |
| 1 | Write synchronization for CTRLA.SWRST bit is ongoing. |