50.6.11 SPI Buffer Register

Table 50-14. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: BUF
Offset: 0x28
Reset: 0x00
Property: PAC Write-Protection

Bit 3130292827262524 
 DATA[31:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 DATA[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 DATA[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 DATA[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:0 – DATA[31:0] FIFO Data bits

Note:
  1. When MODE[32,16] or AUDWD_MODE[1:0] selects 32-bit data, the SPI uses DATA[31:0].
  2. When MODE[32,16] or AUDWD_MODE[1:0] selects 24-bit data, the SPI only uses DATA[24:0].
  3. When MODE[32,16] or AUDWD_MODE[1:0] selects 16-bit data, the SPI only uses DATA[15:0].
  4. When MODE[32,16 ] or AUDWD_MODE[1:0] selects 8-bit data, the SPI only uses DATA[7:0].
  5. The SPI pushes data to the SPIxTXB on the write to the highest byte defined by MODE[32,16] or AUDWD_MODE[1:0]. Likewise, the SPI pops data from the SPIxRXB on the read of the highest byte defined by MODE[32,16] or AUDWD_MODE[1:0]. For instance, if writing data 8-bits at a time in 32-bit mode, the SPI commits data to the SPIxTXB on a write to DATA[31:24]. The SPI does not use or track any other byte write location to determine commitment to the buffer.