50.6.8 SPI Interrupt Enable Clear Register
Note:
- This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
- In TPD mode is recommended to not enable the devices dedicated as clients interrupts. The SPITUREN, SPIROUEN, and FRMERREN for the Clients should all be disabled and only enable the Host's interrupts as needed.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR |
| Offset: | 0x1C |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SPIROVEN | SPITUREN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRMERREN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPITXBEEN | SPIRXBFEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 30 – SPIROVEN Enable Interrupt Events via SPIROV
Writing a zero to this bit has no effect.
Writing a one to this bit will SET the Enable bit.
| Value | Description |
|---|---|
| 0 | Disables Receive Overflow (Does Not) Generates Error Events |
| 1 | Enables Receive Overflow Generates Error Events |
Bit 27 – SPITUREN Enable Interrupt Events via SPITUR
Writing a zero to this bit has no effect.
Writing a one to this bit will SET the Enable bit.
| Value | Description |
|---|---|
| 0 | Disables Transmit Under-run (Does Not) Generates Error Events |
| 1 | Enables Transmit Under-run Generates Error Events |
Bit 15 – FRMERREN Enable Interrupt Events via FRMERR
Writing a zero to this bit has no effect.
Writing a one to this bit will SET the Enable bit.
| Value | Description |
|---|---|
| 0 | Disables Frame Error (Does not) Generates Error Events |
| 1 | Enables Frame Error Generates Error Events |
Bit 4 – SPITXBEEN Enable Interrupt Events via SPITXBE
Writing a zero to this bit has no effect.
Writing a one to this bit will SET the Enable bit.
| Value | Description |
|---|---|
| 0 | Disables (Does Not) Generates TXBE Error Events |
| 1 | Enables Generates TXBE Events |
Bit 0 – SPIRXBFEN Enable Interrupt Events via SPIRXBF
Writing a zero to this bit has no effect.
Writing a one to this bit will SET the Enable bit.
| Value | Description |
|---|---|
| 0 | Disables (Does Not) Generates RXBF Error Events |
| 1 | Enables Generates RXBF Events |