50.6.10 SPI Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS |
| Offset: | 0x24 |
| Reset: | 0x90002000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SPIRBE | SPIRBF | SPITBE | SPITBF | TXBUFELM8 | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 1 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXBUFELM7 | TXBUFELM6 | TXBUFELM5 | TXBUFELM4 | TXBUFELM3 | TXBUFELM2 | TXBUFELM1 | TXBUFELM0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SPIBUSY | SRMT | RXBUFELM8 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 1 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXBUFELM7 | RXBUFELM6 | RXBUFELM5 | RXBUFELM4 | RXBUFELM3 | RXBUFELM2 | RXBUFELM1 | RXBUFELM0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – SPIRBE RX Buffer Empty bit
SPIRBF reflects the empty status of the multi-element FIFO.
| Value | Description |
|---|---|
| 0 | RX Buffer not Empty |
| 1 | RX Buffer Empty |
Bit 29 – SPIRBF SPI Receive Buffer Full status bit
SPIRBF reflects the full status of the multi-element FIFO.
| Value | Description |
|---|---|
| 0 | SPIxRXB is not full |
| 1 | SPIxRXB is full |
Bit 28 – SPITBE SPI Transmit Buffer Empty status bit
SPITBE reflects the empty status of the multi-element FIFO.
| Value | Description |
|---|---|
| 0 | SPIxTXB is not empty |
| 1 | SPIxTXB is empty |
Bit 26 – SPITBF SPI Transmit Buffer Full Status bit
SPITBF reflects the full status of the multi-element FIFO.
| Value | Description |
|---|---|
| 0 | SPIxTXB not full |
| 1 | SPIxTXB is full |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24 – TXBUFELM Transmit Buffer Element Count bits
Reflects the number of FIFO elements used.
8 bit data is 1 element (total of 64 elements available)
8 = 16 bit data is 2 elements (total of 32 elements available)
16 = 24 bit data is 3 elements (total of 21elements available)
24 bit data is 4 elements (total of 16 elements available)
Bit 14 – SPIBUSY SPI activity status bit
| Value | Description |
|---|---|
| 0 | No on-going transactions (at time of read) |
| 1 | Macro currently busy with some transactions |
Bit 13 – SRMT Register (SPIxSR) Empty bit
| Value | Description |
|---|---|
| 0 | There are current or pending transactions. |
| 1 | There are no current or pending transactions. (i.e. Neither SPIxTXB or SPIxSR contain data to transmit) |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8 – RXBUFELM Receive Buffer Element Count bits
Reflects the number of FIFO elements used
8 bit data is 1 element (total of 64 elements available)
8 = 16 bit data is 2 elements (total of 32 elements available)
16 = 24 bit data is 3 elements (total of 21 elements available)
24 bit data is 4 elements (total of 16 elements available)