50.6.3 SPI Control Register

Table 50-6. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bit 10 – SMP SPI Data Input Sample Phase bit

Input data is always sampled at the middle of data output time regardless of the SMP setting in Client Mode.

Value	Description
0	Input data sampled at the middle of data output time in Host Mode
1	Input data sampled at the end of data output time in Host Mode

Value	Description
0	Data from RX FIFO is not sign extended
1	Data from RX FIFO is sign extended

Note:

Value	Description
0	Host Mode: Client select SPI support disabled
1	Host Mode: SPI Client Select support enabled with polarity determined by FRMPOL (SS pin automatically driven during transmission in Host Mode)
0	Client Mode: SS pin used by the macro in Client mode; (SS pin used as client select input)
1	Client Mode: SS pin not used by client mode

Note: Can only be written when Enable =’0’.

Value	Description
0	Client Mode
1	Host Mode

Note: Can only be written when Enable =’0’.

Value	Description
0	SDO pin is controlled by the macro.
1	SDO pin is not used by the macro. Pin controlled by PORT function.

Note: Can only be written when Enable =’0’.

Value	Description
0	SDI pin is controlled by the macro.
1	SDI pin is not used by the macro. Pin controlled by PORT function.

Note:

Note: