25.8.1 Enable

If the user disables the DMA module by clearing the CTRLA.ENABLE bit, care must be taken to ensure that the DMAR and DMAW bus hosts are not frozen in a state that would lock up the Bus Matrix. To this end the current DMAR and DMAW bus transactions shall be completed before honoring the disable request.

Any channel that has its BLKBUSY bit asserted will enter a resumable suspended state. If the user writes to a suspended channel’s SFR register, the channel will reset. See Block Enable for details on a channel reset. The CHCTRLAk.ENABLE bit is also cleared on a channel reset. If the CHCTRLAk.ENABLE bit is set to 1 and a channel is suspended, activity on the channel resumes from the point of suspension.