30.3.9.2 CTRLA SFR Description
The SFR fields that control read operations to the Flash can be changed at any time, provided the FCR (CTRLA specifically) is not write locked by the PAC module. New wait state values are used on the next Flash read. RDBUFWS changes on the next update to the associated read buffer. A new arbitration (ARB) value is used at the next available arbitration cycle on a per panel basis.
ARB
ARB controls read requester arbitration to the Flash. Requesters include each AHB interface (numbered 0 to 2) and the CRC Finite State Machine. The main CPU always uses AHB0 to access the Flash. FCW requests take precedence over read requests. Arbitration is per Flash panel.
When ARB = 0, round-robining arbitration is used for all read requests to the Flash. When ARB = 1, fixed arbitration is used for all reads to the Flash. In this mode, AHB0 has the highest priority followed by AHB1, etc., and CRC has lowest priority.
FWS[3:0] - Flash Wait States
The FWS[3:0] field controls the number of extra clock cycles it takes to access the Flash memory and provide data back (to the bus or internal requester). The number of wait states needed is typically Taws/(AHB Clock Period) rounded up to the nearest integer. If ECC is enabled an extra wait state may be needed. Each device characterizes and states the frequency range for each wait state selection and for ECC on/off. See FLASH CHARACERIZATION.
ADRWS - Address Wait States
The ADRWS field controls the number of extra clock cycles for address setup to the Flash memory. Address wait state occurs before requesting arbitration, so it is in between the bus and the request to Flash. In most system the path starts at the initiator of the request.
When ADRWS = 0, no extra cycle clocks are added to address setup. When ADRWS = 1, one extra clock is added to address setup. ADRWS only affects AHB interfaces. It does nor affect internal read requests such as from CRC logic if present.
AUTOWS - Auto Wait States
The AUTOWS field controls the use of automatic wait state for the Flash access time (Taws). This is useful when varying clock frequencies.
When AUTOWS=1, the total Flash wait states are ADRWS+Taws. When AUTOWS=0 the total Flash wait states are ADRWS+FWS. Non-CPU ports may incur an extra wait state. Note that the bus may add pipeline delays to either the address phase or the data phase.
RDBUFWS[3:0] - Read Buffer Wait States
The RDBUFWS field controls the determinism of accesses from the read buffer. Each bit corresponds to AHB Interface n, n= 0 to 2 When RDBUFWS[n] = 0, AHB interface n returns data from the read buffer in zero wait states. When RDBUFWS[n] = 1, AHB interface n returns data with wait states to match the Flash access of ADRWS+FWS such that the initiator sees a constant access time.
The setting of RDBUFWS is ignored when AUTOWS = 1. For this case, all data return from the read buffer return with zero wait states.