48.5.2.6 Initialization

The following steps must be performed to operate the TRAM module in basic mode:

• Configure the clock source for CLK_TRAM_APB in the Main Clock Controller (MCLK) and enable the clock by writing a ‘1’ to the TRAM bit in the APB Mask register of the MCLK
• Clear all registers by writing ‘1’ to CTRLA.SWRST bit (CTRLA<0>) and wait for the SYNCBUSY.SWRST bit (SYNCBUSY<0>) to set
• Program data scrambling key in DSCC.DSCKEY bits (DSCC <29:0) and enable scrambling by programming DSCEN bit (DSCC <31>)
• Enable the TRAM module by setting CTRLA.ENABLE bit (CTRLA<1>) and wait for the SYNCBUSY.CTRLA bit (SYNCBUSY<1>) to set