48.5.2.9 Data Remanence Prevention

Data remanence prevention can be enabled by setting the CTRLA.DRP (CTRLA <6>) bit. The Data remanence prevention bit (CTRLA.DRP (CTRLA <6>)) must be configured before the CTRLA.ENABLE bit (CTRLA <1> is set. This setting cannot be changed while the module is enabled. When this feature is enabled, the RTC Periodic Interval Event (RTC_PERD) will trigger the automated data remanence routine. An internal counter will count from 0 to 2047 and serves as the address access bus to the security RAM. For every address iteration, the TRAM module reads the word data from the security RAM, inverts the value and writes back to the same address. To prevent linear access to the security RAM, the remanence address value is scrambled using the same protocols as a CPU address scramble. After remanence has updated all address locations, the routine will end by toggling the RAM inversion status bit (RAMINV bit (STATUS <0>)). See the following figure.

Data remanence is a low-priority routine. If the CPU attempts to access the security RAM while remanence is active, the routine is temporarily paused until the CPU access is completed. If a tamper full erase event is detected, the remanence routine is aborted and the internal address counter will reset to 0.