48.5.2.8 Silent Access

Silent access bit (CTRLA.SILACC (CTRLA <7>)) must be configured before CTRLA.ENABLE bit (CTRLA <1>) is set. This setting cannot be changed while the module is enabled. When this mode is enabled, only half of the security RAM (4KB) is available for data storage since the other half is reserved to store the 1's complement (bitwise invert) values.

The TRAM module executes the following protocols:

• When the CPU writes to the security RAM, the data and its bitwise invert are stored into the security RAM.
• When the CPU reads from the security RAM, both the data and its bitwise invert are retrieved from the security RAM. If the TRAM module cannot verify that both values complement each other, a bus error is returned.