36.10.2 USB Control Status Register High for Endpoint0
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CSR0H |
| Offset: | 0x1013 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DISPING | DTWREN | DATATGGL | FLSHFIFO | ||||||
| Access | R/W | R/W/HC | R/W | R/W/HC | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – DISPING Disable Ping tokens control bit
| Value | Description |
|---|---|
| 0 | Ping tokens are issued |
| 1 | USB Module will not issue PING tokens in data and status phases of a Hi-Speed Control transfer |
Bit 2 – DTWREN Data Toggle Write Enable bit
| Value | Description |
|---|---|
| 0 | Disable data toggle write |
| 1 | Enable the current state of the Endpoint 0 data toggle to be written. Automatically cleared. |
Bit 1 – DATATGGL Data Toggle bit
When read, this bit indicates the current state of the Endpoint 0 data toggle.
If DTWREN = 1, this bit is writable with the desired
setting.
If DTWREN = 0, this bit is read-only.
Bit 0 – FLSHFIFO Flush FIFO Control bit
| Value | Description |
|---|---|
| 0 | No Flush operation |
| 1 | Flush
the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO
pointer is reset and theTXPKTRDY/RXPKTRDY bit is cleared. Automatically
cleared when the operation completes. Should only be used when
TXPKTRDY/RXPKTRDY = 1. |