36.10.1 USB Control Status Register Low for Endpoint0
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CSR0L |
| Offset: | 0x1012 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NAKTMOUT | STATUSPKT | REQPKT | ERROR | SETUPPKT | RXSTALL | TXPKTRDY | RXPKTRDY | ||
| Access | R/W/HC | R/W/HC | R/W/HC | R/W/HS | R/W/HS | R/W/HS | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – NAKTMOUT NAK Time-out Control bit
| Value | Description |
|---|---|
| 0 | Allow the endpoint to continue |
| 1 | Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLIM<4:0> bits (USBICSR<28:24>) |
Bit 6 – STATUSPKT Status Stage Transaction Control Bit
| Value | Description |
|---|---|
| 0 | Do not perform a status stage transaction |
| 1 | When set at the same time as the TXPKTRDY or REQPKT bit is set, performs a status stage transaction |
Bit 5 – REQPKT IN Transaction Request Control Bit
| Value | Description |
|---|---|
| 0 | Do not request an IN transaction |
| 1 | Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set. |
Bit 4 – ERROR No Response Error Status bit
| Value | Description |
|---|---|
| 0 | Clear
this flag. Software must write a '0' to this bit to clear
it. |
| 1 | Three attempts have been made to perform a transaction with no response from the peripheral. An interrupt is generated. |
Bit 3 – SETUPPKT Definition bit
| Value | Description |
|---|---|
| 0 | Normal OUT token for the transaction bit 19 |
| 1 | When set at the same time as the TXPKTRDY bit is set, send a SETUP token instead of an OUT token for the transaction. This also clears the Data Toggle. |
Bit 2 – RXSTALL STALL handshake received Status bit
| Value | Description |
|---|---|
| 0 | Software clear of bit |
| 1 | STALL handshake was received |
Bit 1 – TXPKTRDY TX Packet Ready Control bit
| Value | Description |
|---|---|
| 0 | No data packet is ready for transmit |
| 1 | Data packet has been loaded into the FIFO. It is cleared automatically. |
Bit 0 – RXPKTRDY RX Packet Ready Status bit
This bit is cleared by setting the SVCRPR bit.
| Value | Description |
|---|---|
| 0 | No data packet has been received |
| 1 | Data packet has been received. Interrupt is generated (when enabled) when this bit is set. |