SAM L21

47.6.3 Digital to Analog Converter (DAC) Characteristics - 105°C

Table 47-11. Operating Conditions⁽¹⁾
Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
Res	Resolution	-	-	-	12	bits
clk	Internal DAC Clock frequency	-	-	-	12	MHz
fs_dac	Sampling frequency	clk/12, CCTRL=0x0 (Low Power)	-	-	10	ksps
fs_dac	Sampling frequency	clk/12, CCTRL=0x2 (High Power)	-	-	1	Msps
V_OUTmin	Min Output Voltage	-	-	-	0.15	V
V_OUTmax	Max Output Voltage	-	V_DDANA-0.15	-	-	V
V_REF	Reference input	CTRLB.REFSEL[1:0]=0x2 (VREFAB)	1	-	V_DDANA-0.15	V
V_REF	Reference input	CTRLB.REFSEL[1:0]=0x0 (VREFAU)	1	-	V_DDANA	V
C_VREF	External decoupling capacitor	-	-	220	-	nF
C_LOAD	Output capacitor load	-	-	-	50	pF
R_LOAD	Output resistance load	-	5	-	-	kΩ
t_s	Settling time	For reaching ±1LSB of the final value. Step size < 500 LSB - C_load = 50pF	-	-	1	µs
t_{s_FS}	Settling time 0x080 to 0xF7F	For reaching ±1LSB of the final value. Step size from 0% to 100% - C_load = 50pF	-	5	7	µs

Note:

These values are based on simulation. They are not covered by production test limits or characterization.

Table 47-12. Differential Mode⁽¹⁾
Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
INL	Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F	clk=12MHz, V_DDANA=3.0V, External Ref.=2.0V, C_Load=50pF	-	±2.5	±3.5	LSB
INL	Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F	clk=12MHz, V_DDANA=2.0V, internal V_DDANA=2.0V, C_Load=50pF	-	±2.2	±3.0	LSB
DNL	Differential Non Linearity, Best-fit curve from 0x080 to 0xF7F	clk=12MHz, V_DDANA=3.0V, External Ref.=2.0V, C_Load=50pF	-	±2.0	±3.5	LSB
DNL		clk=12MHz, V_DDANA=2.0V, internal V_DDANA=2.0V, C_Load=50pF	-	±1.5	±2.5	LSB
Gerr	Gain Error	External Reference voltage	-	±0.3	±0.8	% FSR
		Internal V_DDANA Reference	-	±0.2	±0.5
		1.0V Internal Reference voltage	-	±1	±3.0
Offerr	Offset Error	External Reference voltage	-	±5.0	±15.0	mV
		Internal V_DDANA Reference	-	±4.0	±15.0
		1.0V Internal Reference voltage	-	±10.0	±30.0
TC_g	Gain Drift		-20	-	20	ppm/°C
TC_o	Offset Drift		-0.05	-0.01	0.05	mV/°C
ENOB	Effective Number Of Bits	Fs=1Ms/s - External Ref - High Power	9.5	10.1	10.7	Bits
SNR	Signal to Noise ratio		58.0	67.0	71.0	dB
THD	Total Harmonic Distortion		-71.0	-64.0	-59.0	dB

Note:

These values are based on characterization.

Table 47-13. Single-Ended Mode⁽¹⁾
Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
INL	Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F	clk=12MHz, V_DDANA=3.0V, External Ref.=2.0V, C_Load=50pF	-	±3	±4.5	LSB
INL	Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F	clk=12MHz, V_DDANA=2.0V, internal V_DDANA=2.0V, C_Load=50pF	-	±2.5	±3.5	LSB
DNL⁽¹⁾	Differential Non Linearity, Best-fit curve from 0x080 to 0xF7F	clk=12MHz, V_DDANA=3.0V, External Ref.=2.0V, C_Load=50pF	-	±3.0	±4.0	LSB
DNL⁽¹⁾		clk=12MHz, V_DDANA=2.0V, internal V_DDANA=2.0V, C_Load=50pF	-	±2.5	±3.5	LSB
Gerr	Gain Error	External Reference voltage	-	±0.3	±0.8	% FSR
		Internal V_DDANA Reference	-	±0.2	±0.5
		1.0V Internal Reference voltage	-	±0.1	±3.0
Offerr	Offset Error	External Reference voltage	-	±5.0	±15.0	mV
		Internal V_DDANA Reference	-	±7.0	±15.0
		1.0V Internal Reference voltage	-	±10.0	±12.0
TC_g	Gain Drift		-20	-	20	ppm/°C
TC_o	Offset Drift		-0.03	-0.05	0.02	mV/°C
ENOB	Effective Number Of Bits	Fs=1Ms/s - External Ref - High Power	9.0	10.0	10.3	Bits
SNR	Signal to Noise ratio		56.0	67.0	68.5	dB
THD	Total Harmonic Distortion		-69.0	-65.0	-55.0	dB

Note:

These values are based on characterization.

Table 47-14. Power Consumption⁽¹⁾
Symbol	Parameters	Conditions	Ta	Min.	Typ.	Max.	Unit
I_DDANA	Differential Mode, DC supply current, 2 output channels - without load	fs=1Msps, CCTRL=0x2, V_REF>2.4V, V_CC=3.3V	Max.105°C Typ.25°C	-	401	587	µA
I_DDANA		fs=10ksps, CCTRL=0x0, V_REF<2.4V, V_CC=3.3V		-	84	189	µA
I_DDANA	Single-Ended Mode, DC supply current, 2 output channels - without load	fs=1Msps, CCTRL=0x2, V_REF>2.4V, V_CC=3.3V		-	297	413	µA
I_DDANA		fs=10ksps, CCTRL=0x0, V_REF<2.4V, V_CC=3.3V		-	53	119	µA

Note: 1.These values are based on characterization.

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