18.8.12 APBD Mask
| Name: | APBDMASK |
| Offset: | 0x20 |
| Reset: | 0x000000FF |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCL | OPAMP | PTC | AC | ADC | TC4 | SERCOM5 | EVSYS | ||
| Access | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 7 – CCL CCL APBD Clock Enable
| Value | Description |
|---|---|
| 0 | The APBD clock for the CCL is stopped. |
| 1 | The APBD clock for the CCL is enabled. |
Bit 6 – OPAMP OPAMP APBD Clock Enable
| Value | Description |
|---|---|
| 0 | The APBD clock for the OPAMP is stopped. |
| 1 | The APBD clock for the OPAMP is enabled. |
Bit 5 – PTC PTC APBD Clock Enable
| Value | Description |
|---|---|
| 0 | The APBD clock for the PTC is stopped. |
| 1 | The APBD clock for the PTC is enabled. |
Bit 4 – AC AC APBD Clock Enable
| Value | Description |
|---|---|
| 0 | The APBD clock for the AC is stopped. |
| 1 | The APBD clock for the AC is enabled. |
Bit 3 – ADC ADC APBD Clock Enable
| Value | Description |
|---|---|
| 0 | The APBD clock for the ADC is stopped. |
| 1 | The APBD clock for the ADC is enabled. |
Bit 2 – TC4 TC4 APBD Clock Enable
| Value | Description |
|---|---|
| 0 | The APBD clock for the TC4 is stopped. |
| 1 | The APBD clock for the TC4 is enabled. |
Bit 1 – SERCOM5 SERCOM5 APBD Clock Enable
| Value | Description |
|---|---|
| 0 | The APBD clock for the SERCOM5 is stopped. |
| 1 | The APBD clock for the SERCOM5 is enabled. |
Bit 0 – EVSYS EVSYS APBD Clock Enable
| Value | Description |
|---|---|
| 0 | The APBD clock for the EVSYS is stopped. |
| 1 | The APBD clock for the EVSYS is enabled. |