18.8.5 CPU Clock Division
| Name: | CPUDIV |
| Offset: | 0x04 |
| Reset: | 0x01 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPUDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 7:0 – CPUDIV[7:0] CPU Clock Division Factor
These bits define the division ratio of the main clock prescaler related to the CPU clock domain.
To ensure correct operation, frequencies must be selected so that FCPU≥ FLP (i.e. LPDIV ≥CPUDIV).
Frequencies must never exceed the specified maximum frequency for each clock domain.
| Value | Name | Description |
|---|---|---|
| 0x01 | DIV1 | Divide by 1 |
| 0x02 | DIV2 | Divide by 2 |
| 0x04 | DIV4 | Divide by 4 |
| 0x08 | DIV8 | Divide by 8 |
| 0x10 | DIV16 | Divide by 16 |
| 0x20 | DIV32 | Divide by 32 |
| 0x40 | DIV64 | Divide by 64 |
| 0x80 | DIV128 | Divide by 128 |
| others | - | Reserved |