18.8.2 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
        CKRDY 
Access R/W 
Reset 0 

Bit 0 – CKRDY Clock Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.

ValueDescription
0 The Clock Ready interrupt is disabled.
1 The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready Interrupt Flag is set.