18.8.6 Low Power Clock Division

Name:	LPDIV
Offset:	0x05
Reset:	0x01
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
	LPDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	1

Bits 7:0 – LPDIV[7:0] Low-Power Clock Division Factor

These bits define the division ratio of the main clock prescaler (2ⁿ) related to the Low Power clock domain. To ensure correct operation, frequencies must be selected so that F_CPU ≥ F_LP ≥ F__BUP (i.e. BUPDIV ≥ LPDIV ≥ CPUDIV). Also, frequencies must never exceed the specified maximum frequency for each clock domain.

Refer to the Maximum Clock Frequencies in the Electrical Characterization section for maximum frequencies in each performance level.

Value	Name	Description
0x01	DIV1	Divide by 1
0x02	DIV2	Divide by 2
0x04	DIV4	Divide by 4
0x08	DIV8	Divide by 8
0x10	DIV16	Divide by 16
0x20	DIV32	Divide by 32
0x40	DIV64	Divide by 64
0x80	DIV128	Divide by 128
others	-	Reserved

SAM L21

18.8.6 Low Power Clock Division

Bits 7:0 – LPDIV[7:0] Low-Power Clock Division Factor