18.8.11 APBC Mask

Name: APBCMASK
Offset: 0x1C
Reset: 0x0000 7FFF
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
  TRNGAESDACTC3TC2TC1TC0 
Access RRRRRRR 
Reset 1111111 
Bit 76543210 
 TCC2TCC1TCC0SERCOM4SERCOM3SERCOM2SERCOM1SERCOM0 
Access RR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bit 14 – TRNG TRNG APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TRNG is stopped.
1 The APBC clock for the TRNG is enabled.

Bit 13 – AES AES APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the AES is stopped.
1 The APBC clock for the AES is enabled.

Bit 12 – DAC DAC APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the DAC is stopped.
1 The APBC clock for the DAC is enabled.

Bit 11 – TC3 TC3 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TC3 is stopped.
1 The APBC clock for the TC3 is enabled.

Bit 10 – TC2 TC2 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TC2 is stopped.
1 The APBC clock for the TC2 is enabled.

Bit 9 – TC1 TC1 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TC1 is stopped.
1 The APBC clock for the TC1 is enabled.

Bit 8 – TC0 TC0 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TC0 is stopped.
1 The APBC clock for the TC0 is enabled.

Bit 7 – TCC2 TCC2 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TCC2 is stopped.
1 The APBC clock for the TCC2 is enabled.

Bit 6 – TCC1 TCC1 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TCC1 is stopped.
1 The APBC clock for the TCC1 is enabled.

Bit 5 – TCC0 TCC0 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TCC0 is stopped.
1 The APBC clock for the TCC0 is enabled.

Bit 4 – SERCOM4 SERCOM4 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the SERCOM4 is stopped.
1 The APBC clock for the SERCOM4 is enabled.

Bit 3 – SERCOM3 SERCOM3 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the SERCOM3 is stopped.
1 The APBC clock for the SERCOM3 is enabled.

Bit 2 – SERCOM2 SERCOM2 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the SERCOM2 is stopped.
1 The APBC clock for the SERCOM2 is enabled.

Bit 1 – SERCOM1 SERCOM1 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the SERCOM1 is stopped.
1 The APBC clock for the SERCOM1 is enabled.

Bit 0 – SERCOM0 SERCOM0 APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the SERCOM0 is stopped.
1 The APBC clock for the SERCOM0 is enabled.