SAM L21

47.8.7 Digital Phase Lock Loop (DPLL) Characteristics - 105°C

Table 47-42. Fractional Digital Phase Lock Loop Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
F_IN	Input Clock Frequency		32	-	2000	kHz
F_OUT	Output frequency	PL2	48	-	96	MHz
F_OUT	Output frequency	PL0	48	-	48	MHz
J_P⁽²⁾	Period Jitter	PL0, F_IN=32kHz @ F_OUT=48MHz	-	1.9	5.0	%
		PL2, F_IN=32kHz @ F_OUT=48MHz	-	1.9	4.0
		PL2, F_IN=32kHz @ F_OUT=96MHz	-	3.3	7.0
		PL0, F_IN=2MHz @ F_OUT=48MHz	-	2.0	8.0
		PL2, F_IN=2MHz @ F_OUT=48MHz	-	2.0	4.0
		PL2, F_IN=2MHz @ F_OUT=96MHz	-	4.2	7.0
T_LOCK⁽²⁾	Lock Time	After startup, time to get lock signal, F_IN=32kHz @ F_OUT=96MHz	-	1	2	ms
T_LOCK⁽²⁾	Lock Time	After startup, time to get lock signal, F_IN=2MHz @ F_OUT=96MHz	-	25	35	µs
Duty⁽¹⁾	Duty Cycle		40	50	60	%

Note:

These values are based on simulation. They are not covered by production test limits or characterization.
These values are based on characterization.

Table 47-43. Power Consumption⁽¹⁾
Symbol	Parameter	Conditions	TA	Min.	Typ.	Max.	Units
I_DD	Current Consumption	Ck=48MHz (PL0)	Max.105°C Typ.25°C	-	454	600	µA
I_DD	Current Consumption	Ck=96MHz (PL2)	Max.105°C Typ.25°C	-	934	1099	µA

Note:

These values are based on characterization.

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