2.3.1.1 Differences Between Execution of SIX and a Normal Instruction

There are some differences between executing instructions normally and using the ICSP SIX command. As a result, the code examples in this specification may not match those for performing the same functions during normal device operation.

The important differences are:

• Two-word instructions require two SIX operations to clock in all of the necessary data.

  Examples of two-word instructions are GOTO and CALL.

• Two-cycle instructions require two SIX operations to complete.

  The first SIX operation shifts in the instruction and begins to execute it. A second SIX operation, which should shift in a NOP to avoid losing data, provides the CPU clocks required to finish executing the instruction.

  Examples of two-cycle instructions are Table Read (TBLRD) and Table Write (TBLWT) instructions.

• Must provide NOP instruction during Stall to account for pipeline changes.

  A CPU Stall occurs when an instruction modifies a register that is used for Indirect Addressing by the instruction immediately following the CPU Stall. During normal operation, the CPU will automatically force a NOP while the new data are read. While using ICSP, the CPU stalls under the same conditions, but an instruction needs to be provided to generate the clocks to get through the Stall cycle. Therefore, any indirect references to a recently modified register should be preceded with a NOP.

  For example, the instructions MOV #0x0, W0, followed by MOV[W0], W1, must have a NOP inserted in between.

  If a two-cycle instruction modifies a register that is used indirectly, it will require two following NOPs: one to execute the second half of the instruction and the other NOP stalls the CPU to correct the pipeline.

  For example, instructions such as TBLWTL [W0++], [W1] should be followed by two NOPs.

• The device Program Counter (PC) continues to automatically increment during ICSP instruction execution, even though the Flash memory is not being used. As a result, the PC may be incremented so that it points to invalid memory locations.

  Examples of invalid memory spaces are unimplemented Flash addresses or the vector space (location: 0x0 to 0x1FF).

  If the PC points to these locations, the device will reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method of achieving this is to perform a “GOTO 0x200” instruction.