39.7.148 Post Processing Configuration Register 0
Name: | LCDC_PPCFG0 |
Offset: | 0x0000056C |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
DLBO | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
BLEN[1:0] | SIF | ||||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit 8 – DLBO Defined Length Burst Only For Channel Bus Transaction
Value | Description |
---|---|
0 |
Undefined length INCR burst is used for 2 and 3 beats burst. |
1 |
Only defined length burst is used (SINGLE, INCR4, INCR8 and INCR16). |
Bits 5:4 – BLEN[1:0] System Bus Burst Length
Value | Name | Description |
---|---|---|
0 | AHB_BLEN_SINGLE |
System bus access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. |
1 | AHB_BLEN_INCR4 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. A system bus INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. |
2 | AHB_BLEN_INCR8 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. A system bus INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. |
3 | AHB_BLEN_INCR16 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. A system bus INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. |
Bit 0 – SIF Source Interface
Value | Description |
---|---|
0 | Post-Processing data is transferred through system bus interface 0. |
1 | Post-Processing data is 0: Post-Processing data is through system bus interface 1. |