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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, Graphics Interface, Ethernet 10/100, IEEE®1588, CAN-FD, USB, AEC-Q100 Grade 2
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17
Standard Boot Strategies
17.5
Boot Configuration
17.5.7
Detailed Memory Boot Procedures
17.5.7.5
QSPI NOR Flash Boot
Description
Features
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Automotive Quality Grade
6
Safety and Security Features
7
Pinout
8
Power Considerations
9
Memories
10
Event System
11
System Controller
12
Peripherals
13
Chip Identifier (CHIPID)
14
Cortex-A5 Processor (ARM)
15
L2 Cache Controller (L2CC)
16
Debug and Test Features
17
Standard Boot Strategies
17.1
Description
17.2
Chip Access Using JTAG Connection
17.3
Flow Diagram
17.4
Chip Setup
17.5
Boot Configuration
17.5.1
Boot Configuration Word
17.5.2
Boot Sequence Controller Configuration Register
Boot Sequence Controller Configuration Register
17.5.3
Backup Registers (BUREG)
17.5.4
Boot Configuration Word
Boot Configuration Word
17.5.5
NVM Boot Sequence
17.5.6
Valid Bootstrap Code Detection
17.5.7
Detailed Memory Boot Procedures
17.5.7.1
NAND Flash Boot: NAND Flash Detection
17.5.7.2
NAND Flash Boot: PMECC Error Detection and Correction
17.5.7.3
SDCard/e.MMC Boot
17.5.7.4
SPI Flash Boot
17.5.7.5
QSPI NOR Flash Boot
17.5.7.5.1
Supported QSPI Memories by Manufacturer
17.5.7.5.2
Hardware Considerations
17.5.7.5.3
Software Considerations
17.5.8
Hardware and Software Constraints
17.6
SAM-BA Monitor
17.7
Fuse Box Controller
18
CPU System Bus Matrix (CPUMX)
19
Matrix (H64MX/H32MX)
20
Special Function Registers (SFR)
21
Special Function Registers Backup (SFRBU)
22
Advanced Interrupt Controller (AIC)
23
Watchdog Timer (WDT)
24
Reset Controller (RSTC)
25
Shutdown Controller (SHDWC)
26
Periodic Interval Timer (PIT)
27
Real-time Clock (RTC)
28
System Controller Write Protection (SYSCWP)
29
Slow Clock Controller (SCKC)
30
Peripheral Touch Controller (PTC)
31
Low Power Asynchronous Receiver (RXLP)
32
Clock Generator
33
Power Management Controller (PMC)
34
Parallel Input/Output Controller (PIO)
35
External Memories
36
DDR-SDRAM Controller (MPDDRC)
37
Static Memory Controller (SMC)
38
DMA Controller (XDMAC)
39
LCD Controller (LCDC)
40
Ethernet MAC (GMAC)
41
USB Device High Speed Port (UDPHS)
42
USB Host High Speed Port (UHPHS)
43
Audio Class D Amplifier (CLASSD)
44
Inter-IC Sound Controller (I2SC)
45
Synchronous Serial Controller (SSC)
46
Two-wire Interface (TWIHS)
47
Flexible Serial Communication Controller (FLEXCOM)
48
Universal Asynchronous Receiver Transmitter (UART)
49
Serial Peripheral Interface (SPI)
50
Quad Serial Peripheral Interface (QSPI)
51
Secure Digital MultiMedia Card Controller (SDMMC)
52
Image Sensor Controller (ISC)
53
Controller Area Network (MCAN)
54
Timer Counter (TC)
55
Pulse Density Modulation Interface Controller (PDMIC)
56
Pulse Width Modulation Controller (PWM)
57
Secure Fuse Controller (SFC)
58
Integrity Check Monitor (ICM)
59
Advanced Encryption Standard Bridge (AESB)
60
Advanced Encryption Standard (AES)
61
Secure Hash Algorithm (SHA)
62
Triple Data Encryption Standard (TDES)
63
True Random Number Generator (TRNG)
64
Analog Comparator Controller (ACC)
65
Security Module (SECUMOD)
66
Analog-to-Digital Controller (ADC)
67
Electrical Characteristics
68
Mechanical Characteristics
69
Marking
70
Ordering Information
71
Revision History
Microchip Information
17.5.7.5 QSPI NOR Flash Boot
