36.4.3 Low-power DDR2-SDRAM Initialization

The initialization sequence is generated by software.

The low-power DDR2-SDRAM devices are initialized by the following sequence:

  1. Program the memory device type in the Memory Device register (MPDDRC_MD).
  2. Program the shift sampling value in the Read Data Path register (MPDDRC_RD_DATA_PATH).
  3. Program MPDDRC_LPDDR2_LPDDR3_DDR3_CAL_MR4, MPDDRC_LPDDR2_LPDDR3_DDR3_TIM_CAL, MPDDRC_IO_CALIBR.
  4. Program features of the low-power DDR2-SDRAM device into and in the Configuration register (MPDDRC_CR) (number of columns, rows, banks, CAS latency and output drive strength) and in the Timing Parameter 0 register/Timing Parameter 1 register (MPDDRC_TPR0/1) (asynchronous timing: TRC, TRAS, etc.).
  5. A NOP command is issued to the low-power DDR2-SDRAM. Program the NOP command in the Mode register (MPDDRC_MR). The application must configure the MODE field to 1 in the MPDDRC_MR. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The clocks which drive the Low-power DDR2-SDRAM devices are now enabled.
  6. A pause of at least 100 ns must be observed before a signal toggle.
  7. A NOP command is issued to the low-power DDR2-SDRAM. Program the NOP command in the MPDDRC_MR. The application must configure the MODE field to 1 in the MPDDRC_MR. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. CKE is now driven high.
  8. A pause of at least 200 μs must be observed before issuing a Reset command.
  9. A Reset command is issued to the low-power DDR2-SDRAM. In MPDDRC_MR, configure the MODE field to 7 and the MRS field to 63. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Reset command is now issued.
  10. A pause of at least tINIT5 must be observed before issuing any commands.
  11. A Calibration command is issued to the low-power DDR2-SDRAM. Program the type of calibration in the Configuration register (MPDDRC_CR): configure the ZQ field to 3. In MPDDRC_MR, configure the MODE field to 7 and the MRS field to 10. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The ZQ Calibration command is now issued. Program the type of calibration in the MPDDRC_CR: configure the ZQ field to 2.
  12. A Mode register Write command is issued to the low-power DDR2-SDRAM. In MPDDRC_MR, configure the MODE field to 7 and the MRS field to 1. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode register Write command is now issued.
  13. A Mode register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to 7 and the MRS field to 2. The Mode register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular CAS latency. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode register Write command is now issued.
  14. A Mode register Write command is issued to the low-power DDR2-SDRAM. In MPDDRC_MR, configure the MODE field to 7 and the MRS field to 3. The Mode register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular Drive Strength and Slew Rate. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode register Write command is now issued.
  15. A Mode register Write command is issued to the low-power DDR2-SDRAM. In MPDDRC_MR configure the MODE field to 7 and the MRS field to 16. Mode register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular Partial Array Self-Refresh (PASR). Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode register Write command is now issued.
  16. In the DDR Configuration register (SFR_DDRCFG), the application must write a ‘1’ to bits 17 and 16 to open the input buffers (refer to section “Special Function Registers (SFR)”).
  17. A NOP command is issued to the low-power DDR2-SDRAM. Program the NOP command in the Mode register (MPDDRC_MR). The application must configure the MODE field to 1 in the MPDDRC_MR. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command.
  18. A Mode register Read command is issued to the low-power DDR2-SDRAM. In MPDDRC_MR, configure the MODE field to 7 and the MRS field to 5. The Mode register Read command cycle is used to read the LPDDR2 Manufacturer ID from the low-power DDR2-SDRAM mode registers. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode register Read command is now issued. The LPDDR2 Manufacturer ID is set in MPDDRC_MD. See MPDDRC Memory Device Register.
  19. A Mode register Read command is issued to the low-power DDR2-SDRAM. In MPDDRC_MR, configure the MODE field to 7 and the MRS field to 6. The Mode register Read command cycle is used to read Revision ID1 from the low-power DDR2-SDRAM mode registers. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode register Read command is now issued. Revision ID1 is set in register MPDDRC_MD. See MPDDRC Memory Device Register.
  20. A Mode register Read command is issued to the low-power DDR2-SDRAM. In MPDDRC_MR, configure the MODE field to 7 and the MRS field to 8. The Mode register Read command cycle is used to read the memory organization (I/O width, Density, Type) from the low-power DDR2-SDRAM mode registers. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode register Read command is now issued. Memory organization is set in register MPDDRC_MD. See MPDDRC Memory Device Register.
  21. A Mode register Read command is issued to the low-power DDR2-SDRAM. In MPDDRC_MR, configure the MODE field to 7 and the MRS field to 0. The Mode register Read command cycle is used to read device information (RZQI, DAI) from the low-power DDR2-SDRAM mode registers. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode register Read command is now issued. Device information RZQI is set in register Timing Calibration (see MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register) and DAI is set in Mode register (see MPDDRC Mode Register).
  22. A Normal Mode command is provided. Program the Normal mode in the MPDDRC_MR. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command.
  23. In the DDR configuration register (SFR_DDRCCFG), the application must write a ‘0’ to bits 17 and 16 to close the input buffers. The buffers are then driven by the HMPDDRC controller.
  24. Write the refresh rate into the COUNT field in the Refresh Timer register (MPDDRC_RTR). To compute the value, see MPDDRC Refresh Timer Register.

After initialization, the low-power DDR2-SDRAM devices are fully functional.