36.7.10 MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Calibration and MR4 Register

This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.

Name:	MPDDRC_LPDDR2_LPDDR3_DDR3_CAL_MR4
Offset:	0x2C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	MR4_READ[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	MR4_READ[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	COUNT_CAL[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	COUNT_CAL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – MR4_READ[15:0] Mode Register 4 Read Interval

MR4_READ defines the time period between MR4 reads (for LPDDR2-SDRAM). The formula is (MR4_READ+1) × t_REF. The value to be loaded depends on the average time between REFRESH commands, t_REF. For example, for an LPDDR2-SDRAM with the time between refresh of 7.8 μs, if the MR4_READ value is 2, the time period between MR4 reads is 23.4 μs.

The LPDDR2-SDRAM and LPDDR3-SDRAM devices feature a temperature sensor whose status can be read from the MR4 register. This sensor can be used to determine an appropriate refresh rate. Temperature sensor data may be read from the MR4 register using the Mode Register Read protocol. The Adjust Refresh Rate bit (ADJ_REF) in the Refresh Timer Register (MPDDRC_RTR) must be written to one to activate these reads.

Bits 15:0 – COUNT_CAL[15:0] LPDDR2 LPDDR3 and DDR3 Calibration Timer Count

This 16-bit field is loaded into a timer which generates the calibration pulse. Each time the calibration pulse is generated, a ZQCS calibration sequence is initiated. The ZQCS Calibration command is used to calibrate DRAM Ron values over PVT. One ZQCS command can effectively correct at least 1.5% of output impedance errors within T_zqcs.

One method for calculating the interval between ZQCS commands gives the temperature (T_driftrate) and voltage (V_driftrate) drift rates to which the SDRAM is subject in the application. The interval could be defined by the following formula:

ZQCorrection/((T_Sens x T_driftrate) + (V_Sens x V_driftrate))

where T_Sens = max(dRONdTM) and V_Sens = max(dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if T_Sens = 0.75%/C, V_Sens = 0.2%/mV, T_driftrate = 1C/sec and V_driftrate = 15 mV/s, then the interval between ZQCS commands is calculated as:

1.5/((0.75 x 1) + (0.2 x 15)) = 0.4s

In this example, the devices require a calibration every 0.4s. The value to be loaded depends on the average time between the REFRESH commands, t_REF. For example, for a device with the time between refresh of 7.8 μs, the value of the COUNT_CAL field is programmed as follows: (0.4/7.8 x 10^-6) = 0xC852.

T_Sens and V_Sens are provided by the manufacturer (Output Driver Sensitivity definition). T_driftrate and V_driftrate are defined by the end user.