36.7.2 MPDDRC Refresh Timer Register
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
| Name: | MPDDRC_RTR |
| Offset: | 0x04 |
| Reset: | 0x00300000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MR4_VALUE[2:0] | REF_PB | ADJ_REF | |||||||
| Access | R | R | R | R/W | R/W | ||||
| Reset | 0 | 1 | 1 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COUNT[11:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COUNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 22:20 – MR4_VALUE[2:0] Content of MR4 Register (read-only)
This field gives the content of the MR4 register. This field is updated when MRR command is generated and the Adjust Refresh Rate bit is enabled. An update is done when the read value is different from MR4_VALUE.
To comply with low-power DDR2-SDRAM and low-power DDR3 SDRAM JEDEC memory standards, the LPDDR2/LPDDR3 AC timings (tRCD, tRC, tRAS, tRP and tRRD) must be derated when the MR4 value is 6. If the application needs to work in extreme conditions, the derating value must be added to AC timings before the power-up sequence.
This mode is unique to low-power DDR2-SDRAM devices and low-power DDR3-SDRAM devices.
Bit 17 – REF_PB Refresh Per Bank
This mode is unique to the low-power DDR2-SDRAM devices and low-power DDR3-SDRAM devices.
| Value | Description |
|---|---|
| 0 |
Refresh all banks during auto-refresh operation. |
| 1 |
Refresh the scheduled bank by the bank counter in the memory interface. |
Bit 16 – ADJ_REF Adjust Refresh Rate
This mode is unique to the low-power DDR2-SDRAM devices and low-power DDR3-SDRAM devices.
| Value | Description |
|---|---|
| 0 |
Adjust refresh rate is not enabled. |
| 1 |
Adjust refresh rate is enabled. |
Bits 11:0 – COUNT[11:0] MPDDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh sequence is initiated.
The SDRAM requires auto-refresh cycles at an average periodic interval of Trefi. The value to be loaded depends on the MPDDRC clock frequency MCK (main system bus clock) and average periodic interval of Trefi.
For example, for an SDRAM with Trefi = 7.8 μs and a 133 MHz (7.5 ns) main system bus clock, the value of the COUNT field is configured: ((7.8 × 10-6) / (7.5 × 10-9)) = 1040 or 0x0410.
Low-power DDR2-SDRAM and low-power DDR3-SDRAM devices support Per Bank Refresh operation. In this configuration, average time between refresh command is 0.975 μs. The value of the COUNT field is configured depending on this value. For example, the value of a 133 MHz main system bus clock refresh timer is 130 or 0x82.