33.4 Main System Bus Clock Controller

The Main System Bus Clock Controller provides selection and division of the Main System Bus clock (MCK). MCK is the source clock of the peripheral clocks.

The Main System Bus clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow clock provides a Slow clock signal to the whole device. Selecting the Main clock saves power consumption of the PLLs.

The Main System Bus Clock Controller is made up of a clock selector and a prescaler. It also contains a Main System Bus clock divider which allows the processor clock to be faster than the Main System Bus clock.

The Main System Bus clock selection is made by writing the CSS (Clock Source Selection) field in the Main System Bus Clock register (PMC_MCKR). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 6. PMC_MCKR.PRES programs the prescaler.

Note: It is forbidden to modify MDIV and CSS at the same access. Each field must be modified separately with a wait for MCKRDY flag between the first field modification and the second field modification.

Each time PMC_MCKR is written to define a new Main System Bus clock, PMC_SR.MCKRDY is cleared. It reads 0 until the Main System Bus clock is established. Then, MCKRDY is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done.

Figure 33-2. Main System Bus Clock Controller