33.21 Register Write Protection

To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PMC Write Protection Mode register (PMC_WPMR).

If a write access to a write-protected register is detected, the WPVS bit in the PMC Write Protection Status register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.

The WPVS bit is automatically cleared after reading PMC_WPSR.

The following registers can be write-protected:

• PMC System Clock Enable Register
• PMC System Clock Disable Register
• PMC Peripheral Clock Enable Register 0
• PMC Peripheral Clock Disable Register 0
• PMC Clock Generator Main Oscillator Register
• PMC Clock Generator Main Clock Frequency Register
• PMC Clock Generator PLLA Register
• PMC Main System Bus Clock Register
• PMC USB Clock Register
• PMC Programmable Clock Register
• PMC Fast Startup Polarity Register
• PMC Fast Startup Mode Register
• PLL Charge Pump Current Register
• PMC Asynchronous Partial Wake-Up Enable Register 0
• PMC Asynchronous Partial Wake-Up Disable Register 1
• PMC Asynchronous Partial Wake-Up Enable Register 1
• PMC Asynchronous Partial Wake-Up Disable Register 1
• PMC Asynchronous Partial Wake-Up Control Register