33.19 Programming Sequence

  1. If the 8 to 24 MHz crystal oscillator is not required, PLL can be directly configured (begin with Step 6. or Step 7.) else this oscillator must be started (begin with Step 2.).
  2. Enable the 8 to 24 MHz crystal oscillator by setting CKGR_MOR.MOSCXTEN. The user can define a start-up time. This can be achieved by writing a value in CKGR_MOR.MOSCXTST. Once this register has been correctly configured, the user must wait for PMC_SR.MOSCXTS to be set. This can be done either by polling MOSCXTS or by waiting for the interrupt line to be raised if the associated interrupt source (MOSCXTS) has been enabled in PMC_IER.
  3. Switch the MAINCK to the 8 to 24 MHz crystal oscillator by setting CKGR_MOR.MOSCSEL.
  4. Wait for PMC_SR.MOSCSELS to be set to ensure the switchover is complete.
  5. Check the Main clock frequency:

    The Main clock frequency can be measured via CKGR_MCFR.

    Read CKGR_MCFR until CKGR_MCFR.MAINFRDY is set, after which the user can read CKGR_MCFR.MAINF by performing an additional read. This provides the number of Main clock cycles that have been counted during a period of 16 Slow clock cycles.

    If MAINF = 0, switch the MAINCK to the 12 MHz RC oscillator by clearing CKGR_MOR.MOSCSEL. If MAINF ≠ 0, proceed to Step 6.

  6. Set the PLLA and divider (if not required, proceed to Step 7.)

    All parameters needed to configure PLLA and the divider are located in CKGR_PLLAR.

    The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 127. If MULA is cleared, PLLA is turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by (MULA + 1).

    The PLLACOUNT field specifies the number of Slow clock cycles before PMC_SR.LOCKA is set after CKGR_PLLAR has been written.

    Once CKGR_PLLAR has been written, the user must wait for PMC_SR.LOCKA to be set. This can be done either by polling LOCKA in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKA) has been enabled in PMC_IER. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage parameter MULA or DIVA is modified, LOCKA goes low to indicate that PLLA is not yet ready. When PLLA is locked, LOCKA is set again.

    The user must wait for the LOCKA to be set before using the PLLA output clock.

  7. Set High-speed PLL (UPLL) for UTMI.

    The UTMI PLL is enabled by setting CKGR_UCKR.UPLLEN. The PLL start-up time is configured by writing a value in CKGR_UCKR.PLLCOUNT.

    Once this register has been correctly configured, the user must wait for PMC_SR.LOCKU to be set. This can be done either by polling LOCKU in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKU) has been enabled in PMC_IER.

  8. Select Main System Bus Clock and Processor Clock

    The Main System Bus clock and the Processor clock are configurable via PMC_MCKR.

    The CSS field is used to select the clock source of the Main System Bus clock and Processor clock dividers. By default, the selected clock source is the Main clock.

    The PRES field is used to define the Processor clock and Main System Bus clock prescaler. The user can choose between different values from 1 to 256). Prescaler output is the selected clock source frequency divided by the PRES value.

    The MDIV field is used to define the Main System Bus clock divider. It is possible to choose between different values (0, 1, 2, 3). The Main System Bus clock output is Processor clock frequency divided by 1, 2, 3 or 4, depending on the value programmed in MDIV.

    The PMC PLLA clock input must be divided by 2 by writing the PLLADIV2 if MDIV is set to 3.

    By default, MDIV and PLLLADIV2 are cleared, which indicates that Processor clock is equal to the Main System Bus clock.

    Once PMC_MCKR has been written, the user must wait for PMC_SR.MCKRDY to be set. This can be done either by polling MCKRDY in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (MCKRDY) has been enabled in PMC_IER.

    PMC_MCKR must not be programmed in a single write operation. The programming sequence for PMC_MCKR is the following:

    If a new value for CSS field corresponds to PLL clock,

    a. Program PMC_MCKR.PRES.

    b. Wait for PMC_SR.MCKRDY to be set.

    c. Program PMC_MCKR.MDIV.

    d. Wait for PMC_SR.MCKRDY to be set.

    e. Program PMC_MCKR.CSS.

    f. Wait for PMC_SR.MCKRDY to be set.

    If a new value for CSS field corresponds to Main clock or Slow clock,

    a. Program PMC_MCKR.CSS.

    b. Wait for PMC_SR.MCKRDY to be set.

    c. Program PMC_MCKR.PRES.

    d. Wait for PMC_SR.MCKRDY to be set.

    If CSS, MDIV or PRES are modified at some stage, MCKRDY goes low to indicate that the Main System Bus clock and the Processor clock are not yet ready. The user must wait for the MCKRDY bit to be set again before using the Main System Bus and Processor clocks.

    Note: If PLLA clock was selected as the Main System Bus clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag goes low while PLL is unlocked. Once PLL is locked again, LOCKA goes high and MCKRDY is set.
 While PLL is unlocked, the Main System Bus clock selection is automatically changed to Slow clock. For further information, see Clock Switching Waveforms.

    Code Example:

    write_register(PMC_MCKR,0x00000001)

    wait (MCKRDY=1)

    write_register(PMC_MCKR,0x00000011)

    wait (MCKRDY=1)

    The Main System Bus clock is Main clock divided by 2.

    The Processor clock is the Main System Bus clock.

  9. Select Programmable Clocks

    Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Three programmable clocks can be used. PMC_SCSR indicates which programmable clock is enabled. By default all programmable clocks are disabled.

    PMC_PCKx registers are used to configure programmable clocks.

    The PMC_PCKx.CSS field selects the programmable clock divider source. Five clock options are available: Main clock, Slow clock, Main System Bus clock, PLLACK, UPLLCK. The Slow clock is the default clock source.

    The PRES field is used to control the programmable clock prescaler. It is possible to choose among different values (from 1 to 256). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES value is cleared which means that PCKx is equal to Slow clock.

    Once the PMC_PCKx register has been configured, the corresponding programmable clock must be enabled and the user is constrained to wait for PMC_SR.PCKRDYx to be set. This can be done either by polling PMC_SR.PCKRDYx or by waiting for the interrupt line to be raised if the associated interrupt source (PCKRDYx) has been enabled in PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation.

    If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable clock and wait for PCKRDYx to be set.

  10. Enable Peripheral Clocks

    Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via PMC_PCERx and PMC_PCDRx.