33.13 DDR2/LPDDR/LPDDR2 Clock Controller

The PMC controls the clocks of the DDR memory.

The DDR clock can be enabled and disabled with PMC_SCER.DDRCK and PMC_SDER.DDRCK, respectively. At reset, the DDR clock is disabled to reduce power consumption.

If PMC_MCKR.MDIV = 0 (PCK = MCK), the DDR clock is not available.

To reduce PLLA power consumption, the user can choose UPLLCK as an input clock for the system. In this case, the DDR Controller can drive LPDDR or LPDDR2 at up to 120 MHz.