8.3 Power Management Unit

The Microchip SAMA7G54 System-On-Module is supplied by an external supply (5V_MAIN) and generates its own internal supplies by interfacing with the Microchip MCP16502 Power Management Unit.

The MCP16502 is a fully-featured Power Management Integrated Circuit (PMIC), cost and size-optimized for Microchip MPU devices such as SAMA7G54.

The MCP16502 integrates four DC-DC buck regulators used for system supplying and two auxiliary LDOs for customer purpose.

All buck channels can support loads up to 1A. All bucks are 100% duty cycle capable.
- Buck 1 (VDD_3V3) set to 3.3 V supplies all pads of the embedded devices. This power rail offers a 600-mA load to customer applications through VDD_3V3 (pin 173).
- Buck 2 (VDDIODDR) set to 1.35V supplies the DDR3L memory. It is used internally only.
- Buck 3 (VDDCORE) set to 1.15V supplies the microprocessor core. It is used internally only.
- Buck 4 (VDDCPU) set to 1.15V/1.25V supplies the microprocessor CPU. It is used internally only.
One 300 mA LDO is provided so that sensitive analog loads can be supported. The LDO output voltage, named VLDO1 (pin 11), is configured by a three-state pin named SEL_VLDO1 (pin 8) at power-up and can deliver 1.8V, 2.5V or 3.3V. Other voltage values can be reached after system initialization by an I²C interface access.
One 300 mA LDO is provided so that sensitive analog loads can be supported. The LDO output voltage, named VLDO2 (pin 12), is disabled by default at power-up. Output voltage values are set through an I²C interface access after system initialization.

The default power channel sequencing is built-in, as required by the Microchip SAMA7G54 MPU device.

Active discharge resistors are provided on each output. All buck channels support safe start-up into pre-biased outputs.

The MCP16502 is available in a 5x5 mm 32-pin VQFN package.

For more information, refer to the MCP16502 data sheet (see Reference Documents).

The SEL_VLDO1 pin is meant to program the default settings of the VLDO1 power rail, which must be activated during the power-up sequence. It cannot be managed dynamically by the host.

The default value is selectable among three options corresponding to three different states of the relevant pin: connected to ground (Low), connected to input supply (High) or left unconnected (High-Z).

The VLDO1 default voltage can be selected by means of the SEL_VLDO1 pin, as shown in the table below.

Table 8-4. VLDO1 Voltage vs. SEL_VLDO1 Pin
SEL_VLDO1 Status	VLDO1 Output Voltage
Low	1.8V
High-Z	2.5V
High	3.3V

The LPM pin of the Microchip SAMA7G54 System-On-Module, combined with the HPM and PWRHLD status pins of the MCP16502 PMIC, defines different power states, which are illustrated in Table 8-5.

Note: LPM is controlled by the MPU, and HPM is controlled externally. For more information, refer to the MCP16502 data sheet (see Reference Documents).

Table 8-5. MCP16502 Default Power States
PWRHLD	LPM	HPM	Buck1	Buck2	Buck3	Buck4	LDO1	LDO2	nRST	Power State⁽¹⁾
0	0	0	Off	Off	Off	Off	Off	Off	Low	Off
0	1	0	Off	On⁽²⁾	Off	On⁽²⁾	Off	Off	Low	Hibernate mode
1	1	0	On⁽²⁾	On⁽²⁾	On⁽²⁾	On⁽²⁾	On	Off	HiZ	Low-Power mode
1	0	0	On⁽³⁾	On⁽³⁾	On⁽³⁾	On⁽³⁾	On	Off	HiZ	Active mode
1	0	1	On⁽³⁾	On⁽³⁾	On⁽³⁾	On⁽³⁾	On	Off	HiZ	High Performance Active mode

Note:

Only allowed modes are listed. If some PWRHLD/LPM/HPM combination is not listed, the mode is not allowed.
In this mode, the DCDC is configured in Automatic Pulse-Frequency Modulation (Auto-PFM) mode.
In this mode, the DCDC is configured in Force Pulse-Width Modulation (FPWM) mode.

For more information about the use of the MCP16502 PMIC LPM feature, refer to the MCP16502 data sheet (see Reference Documents).