8.2 Power-Up/Power-Down Considerations

At power-up, from a power supply sequencing perspective, the SAMA7G54 SOM Series power supplies are categorized into six independent groups:

5V_MAIN (main supply)
VBAT (backup supply)
VDD_3V3 (internal periphery group) containing VDDIN33, VDDIOP1, VDDSDMMC2 and VDDQSPI1 supplies
VDDIODDR supply (internal memory group)
VDDQSPI0, VDDIOP0, VDDSDMMC0 and VDDSDMMC1 input supplies (external periphery group)
VDDCORE and VDDCPU supplies (core group)

Figure 8-2 shows the recommended power-up sequence.

Note:

VBAT
- When supplied from a precharged storage element (battery, supercapacitor or micro-battery), VBAT is an always-on supply input and is therefore not part of the power supply sequencing.
- When no storage element is used on VBAT in the application, VBAT must be tied to VDD_3V3.
- When a supercapacitor or a micro-battery is used in the application to power VBAT in Backup mode, this element must be isolated from VBAT during its (slow) charge, so that VBAT closely follows VDD_3V3. In Table 8-2, the parameter t₁ limits the delay to establish VBAT after VDD_3V3.
VDDOUT25 is the output of the internal 2.5V regulator and therefore there is no power supply requirement on this pin. VDDOUT25 is automatically started when VDD_3V3 is above its Power-On Reset threshold.

Figure 8-2. Recommended Power-Up Sequence

Note:

If one or all VDDQSPI0, VDDIOP0, VDDSDMMC0 and VDDSDMMC1 are supplied externally, the power must be applied at the same time or after the presence of VDD_3V3.
VLDO1 is started at the same time as VDD_3V3. It is the default state at the first start-up. The VLDO1 “On” condition can be changed by the I²C interface.

Table 8-2. Power-Up Timing Requirements
Symbol	Parameter	Conditions⁽¹⁾	Min	Typ⁽²⁾	Max	Unit
t₀	NSTART_SOM deglitch time	NSTART_SOM pin falling edge	0.5	–	–	ms
t₁	VBAT delay	Delay from established VDD_3V3 to established VBAT	–	–	0.2	ms
t₂⁽²⁾	VDD_3V3 to Periphery group delay	Delay from established VDD_3V3 to the periphery group established supply	–	8	–	ms
t₃⁽²⁾	Periphery group to VDDCORE/VDDCPU delay	Delay from the periphery group established supply to the VDDCORE and VDDCPU supplies turn-on	–	4	–	ms
t₄⁽²⁾	Reset delay at power-up	From established VDDCORE/VDDCPU to NRST high	–	16	–	ms

Note:

The term "established" refers to a power supply having reached 90% of its final value.
t₂, t₃ and t₄ can be configured after the first start-up by interfacing with PMIC on the I²C interface.

The following figure shows the SAMA7G54 SOM Series power-down sequence that starts by asserting the NRST line to 0.

Once NRST is asserted, the supply inputs can be immediately shut down without any specific timing or order. VBAT may not be shut down if the application uses a backup storage element on this supply input.

Figure 8-3. Recommended Power-Down Sequence

Table 8-3. Power-Down Timing Requirements
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
t_RSTPD	NRST delay at power-down	Delay from NRST asserted to first supply turn-off	0	–	–	ms