15.2.4 Digital Frequency Correction

The RTC module contains Digital Frequency Correction logic to compensate for inaccurate source clock frequencies which would otherwise result in skewed time measurements. The correction scheme requires that at least two bits in the RTC module prescaler are reserved by the correction logic. As a result of this implementation, frequency correction is only available when the RTC is running from a 1Hz reference clock.

The correction procedure is implemented by subtracting or adding a single cycle from the RTC prescaler every 1024 RTC Generic Clock (GCLK) cycles. The adjustment is applied the specified number of time (maximum 127) over 976 of these periods. The corresponding correction in parts per million (PPM) will be given by:

C o r r e c t i o n ( P P M ) = V A L U E 999424 1 0 6

The RTC clock will tick faster if provided with a positive correction value, and slower when given a negative correction value.