2 Bank Locations

RT PolarFire FPGA I/Os are grouped based on I/O voltage standards and I/O capabilities. Each I/O bank has dedicated I/O supplies and ground voltages. Because of these dedicated supplies, only I/O with compatible standards are assigned to the same I/O voltage bank.

The following illustration shows the bank locations for the RTPF500T device with available package combinations.

Figure 2-1. RT PolarFire® RTPF500T-CG1509 I/O Bank Locations
The following table lists the organization of the I/O banks in RT PolarFire FPGAs. Each XCVR supports four lanes in every package. In all the packages, PCIe® is supported only in XCVR0.
Table 2-1. Organization of I/O Banks
Bank NumberCG1509
RTPF500T
Bank 0HSIO
Bank 1HSIO
Bank 2GPIO
Bank 3JTAG/FIXED I/O
Bank 4GPIO
Bank 5GPIO
Bank 6HSIO
Bank 7HSIO
XCVR 0Included
XCVR 1Included
XCVR 2Included
XCVR 3Included
XCVR 4Included
XCVR 5Included

Each I/O bank supports multiple DDR lanes. If CDR/SGMII interface is connected to the I/O bank, the Tx and Rx signal must be within the same DDR Lane. Only one CDR/SGMII is allowed per DDR lane.

For more information about DDR lanes for each package in Package Pin Assignment Table (PPAT), see RT PolarFire FPGA Product Overview.

The following table lists the XCVR channels for RT PolarFire device/package.
Table 2-2. Serial Transceiver Channels
DeviceCG1509
RTPF500T24