10 Appendix 6: References
(Ask a Question)This section lists documents that provide more information about the PCIe EndPoint and IP cores used in the reference design.
- For more information about PolarFire transceiver blocks, PF_TX_PLL and PF_XCVR_REF_CLK, see PolarFire Family Transceiver User Guide .
- For more information about PF_PCIE, see PolarFire Family PCI Express User Guide .
- Fore more information about PF_CCC, see PolarFire Family Clocking Resources User Guide .
- Fore more information about DDR3L/DDR4 memory, see PolarFire Family Memory Controller User Guide .
- For more information about Libero, ModelSim and Synplify, see the Libero SoC Documentation web page.
- For more information about PolarFire FPGA Evaluation Kit, see UG0747: PolarFire FPGA Evaluation Kit User Guide
- For more information about PolarFire FPGA Splash Kit, see UG0786: PolarFire FPGA Splash Kit User Guide
- For more information about CoreAHBLite, see CoreAHBLite Handbook. This user guide can be downloaded from the Libero SoC Catalog.
- For more information about CoreAHBtoAPB3, see CoreAHBtoAPB3 Handbook. This user guide can be downloaded from the Libero SoC Catalog.
- For more information about CoreUART, see CoreUART User Guide. This user guide can be downloaded from the Libero SoC Catalog.