1 PolarFire FPGA PCIe EndPoint, DDR3L, and DDR4 Memory Controller Data Plane

This document explains how to use the accompanying reference design to demonstrate the high-speed data transfer capability of the PolarFire FPGA using the hardened PCIe EndPoint, Soft DDR3L and DDR4 controller IP. The PCIe controller, built-in Direct Memory Access (DMA) controller, and the CoreAXI4DMAController IP are used to achieve high-speed, bulk data transfers, as follows:

  • The PCIe controller’s built-in DMA controller performs bulk-data transfer between contiguous/scatter gather memory locations on a host PC and contiguous memory locations of DDR3L/DDR4/LSRAM.
  • The CoreAXI4DMAController performs data transfers between DDR3L/DDR4 memory and LSRAM using the CoreAXI4DMAController.

The demo also shows how to use pre-synthesized design simulations using PCIe BFM script to initiate the PCIe EndPoint DMA to perform data transfers between LSRAM, DDR3L, DDR4 and PCIe.

This design can be used with a host PC running either Windows® 10.0 or Linux® 6.8 (Ubuntu). The Windows® 10 kernel-mode PCIe device driver, developed using the Windows Driver Kit (WDK) platform, interacts with the PolarFire PCIe EndPoint from the host PC. A Graphic User Interface (GUI) application that runs on the host PC is provided to set up and initiate the DMA transactions between the host PC memory, DDR3L, DDR4 and the LSRAM memories of the PolarFire Evaluation/Splash kit through the PCIe interface.

A user application interface is provided for the GUI to interact with the PCIe driver. The GUI can also initiate the DMA transactions between DDR3L/DDR4 and LSRAM through UART IF. If the host PC PCIe slot is not available, the DMA between DDR3L/DDR4 and LSRAM is exercised through UART IF.

The PCIe EndPoint reference design can be programmed using the job file: To program the device using the job file provided along with the design files, see Appendix 4: Programming the Device Using FlashPro Express.
Important: The user can debug the PCIe features: PCIe lane status, LTSSM state machine and other available PCIe features using SmartDebug. For more information about PCIE Debug using SmartDebug, see SmartDebug User Guide .