PIC18F26/45/46Q10

21.9.5 TxCLKCON

Timer Clock Source Selection Register

Name:	TxCLKCON
Address:	0xFBE,0xFB8,0xFB2


Bit	7	6	5	4	3	2	1	0
				CS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CS[4:0] Timer Clock Source Selection bits

Table 21-3. Clock Source Selection
CS[4:0]	Clock Source
CS[4:0]	Timer2	Timer4	Timer6
`11111-11000`	Reserved	Reserved	Reserved
`10111`	CLC8_out	CLC8_out	CLC8_out
`10110`	CLC7_out	CLC7_out	CLC7_out
`10101`	CLC6_out	CLC6_out	CLC6_out
`10100`	CLC5_out	CLC5_out	CLC5_out
`10011`	CLC4_out	CLC4_out	CLC4_out
`10010`	CLC3_out	CLC3_out	CLC3_out
`10001`	CLC2_out	CLC2_out	CLC2_out
`10000`	CLC1_out	CLC1_out	CLC1_out
`01111-01001`	Reserved	Reserved	Reserved
`01000`	ZCD_OUT	ZCD_OUT	ZCD_OUT
`00111`	CLKREF_OUT	CLKREF_OUT	CLKREF_OUT
`00110`	SOSC	SOSC	SOSC
`00101`	MFINTOSC (31 kHz)	MFINTOSC (31 kHz)	MFINTOSC (31 kHz)
`00100`	LFINTOSC	LFINTOSC	LFINTOSC
`00011`	HFINTOSC	HFINTOSC	HFINTOSC
`00010`	F_OSC	F_OSC	F_OSC
`00001`	F_OSC/4	F_OSC/4	F_OSC/4
`00000`	Pin selected by T2INPPS	Pin selected by T4INPPS	Pin selected by T6INPPS

Value	Description
n	See the “Clock Source Selection” table

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