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20.14.3 TMRxCLK Timer Clock Source
Selection Register Name: TMRxCLK Address: 0xFD1,0xFCB,0xFC5
Bit 7 6 5 4 3 2 1 0 CS[4:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0
Bits 4:0 – CS[4:0] Timer Clock Source Selection
bits
Table 20-4. Timer Clock Sources CS Clock Source Timer1 Timer3 Timer5 11000-11111Reserved Reserved Reserved 10111CLC8_out CLC8_out CLC8_out 10110CLC7_out CLC7_out CLC7_out 10101CLC6_out CLC6_out CLC6_out 10100CLC5_out CLC5_out CLC5_out 10011CLC4_out CLC4_out CLC4_out 10010CLC3_out CLC3_out CLC3_out 10001CLC2_out CLC2_out CLC2_out 10000CLC1_out CLC1_out CLC1_out 01111-01100Reserved Reserved Reserved 01011TMR5
overflow TMR5
overflow Reserved 01010TMR3
overflow Reserved TMR3
overflow 01001Reserved TMR1
overflow TMR1
overflow 01000TMR0
overflow TMR0
overflow TMR0
overflow 00111CLKREF CLKREF CLKREF 00110SOSC SOSC SOSC 00101MFINTOSC (500
kHz) MFINTOSC (500
kHz) MFINTOSC (500
kHz) 00100LFINTOSC LFINTOSC LFINTOSC 00011HFINTOSC HFINTOSC HFINTOSC 00010FOSC FOSC FOSC 00001FOSC /4 FOSC /4 FOSC /4 00000T1CKIPPS T3CKIPPS T5CKIPPS
Reset States: POR/BOR = 00000 All Other Resets = uuuuu
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