18.1 PPS Inputs

Each peripheral has an xxxPPS register with which the input pin to the peripheral is selected. Not all ports are available for input as shown in the following table.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Important: The notation “xxx” in the generic register name is a place holder for the peripheral identifier. For example, xxx = INT for the INTPPS register.
Table 18-1. PPS Input Selection Register Details
PeripheralPPS Input RegisterDefault Pin Selection
 at PORRegister Reset Value
 at PORPORT From Which Input Is Available
28-Pin Devices40-Pin Devices
Interrupt 0INT0PPSRB00x08ABAB
Interrupt 1INT1PPSRB10x09ABAB
Interrupt 2INT2PPSRB20x0AABAB
Timer0 ClockT0CKIPPSRA40x04ABAB
Timer1 ClockT1CKIPPSRC00x10ACAC
Timer1 GateT1GPPSRB50x0DBCBC
Timer3 ClockT3CKIPPSRC00x10BCBC
Timer3 GateT3GPPSRC00x10ACAC
Timer5 ClockT5CKIPPSRC20x12ACAC
Timer5 GateT5GPPSRB40x0CBCBD
Timer2 ClockT2INPPSRC30x13ACAC
Timer4 ClockT4INPPSRC50x15BCBC
Timer6 ClockT6INPPSRB70x0FBCBD
ADC Conversion TriggerADACTPPSRB40x0CBCBD
CCP1CCP1PPSRC20x12BCBC
CCP2CCP2PPSRC10x11BCBC
CWGCWG1PPSRB00x08BCBD
DSM Carrier LowMDCARLPPSRA30x03ACAD
DSM Carrier HighMDCARHPPSRA40x04ACAD
DSM SourceMDSRCPPSRA50x05ACAD
EUSART1 ReceiveRX1PPSRC70x17BCBC
EUSART1 ClockCK1PPSRC60x16BCBC
EUSART2 ReceiveRX2PPSRB70x0FBCBD
EUSART2 ClockCK2PPSRB60x0EBCBD
MSSP1 ClockSSP1CLKPPSRC30x13BCBC
MSSP1 DataSSP1DATPPSRC40x14BCBC
MSSP1 Client SelectSSP1SSPPSRA50x05ACAD
MSSP2 ClockSSP2CLKPPSRB10x09BCBD
MSSP2 DataSSP2DATPPSRB20x0ABCBD
MSSP2 Client SelectSSP2SSPPSRB00x08BCBD
CLCIN0CLCIN0PPSRA00x00ACAC
CLCIN1CLCIN1PPSRA10x01ACAC
CLCIN2CLCIN2PPSRB60x0EBCBD
CLCIN3CLCIN3PPSRB70x0FBCBD
CLCIN4CLCIN4PPSRA00x00ACAC
CLCIN5CLCIN5PPSRA10x01ACAC
CLCIN6CLCIN6PPSRB60x0EBCBD
CLCIN7CLCIN7PPSRB70x0FBCBD