33.7.5 ADSTAT

ADC Status Register
Note:
  1. If ADCS = 1, and FOSC < FRC, the indicated status may not be valid.
  2. If ADC clock source is ADCRC and FOSC < ADRC, the indicated status may not be valid.
  3. STAT = 'b100 appears between the two triggers when DSEN = 1 and CONT = 0.
Name: ADSTAT
Address: 0xF60

Bit 76543210 
 ADAOVADUTHRADLTHRADMATH ADSTAT[2:0] 
Access R/C/HS/HCROROR/C/HS/HCRORORO 
Reset 0000000 

Bit 7 – ADAOV ADC Accumulator Overflow bit

ValueDescription
1 ADC accumulator or ADERR calculation have overflowed
0 ADC accumulator and ADERR calculation have not overflowed

Bit 6 – ADUTHR ADC Module Greater-than Upper Threshold Flag bit

ValueDescription
1 ADERR > ADUTH
0 ADERR ≤ ADUTH

Bit 5 – ADLTHR ADC Module Less-than Lower Threshold Flag bit

ValueDescription
1 ADERR < ADLTH
0 ADERR ≥ ADLTH

Bit 4 – ADMATH ADC Module Computation Status bit

ValueDescription
1 Registers ADACC, ADFLTR, ADUTH, ADLTH and the ADAOV bit are updating or have already updated
0 Associated registers/bits have not changed since this bit was last cleared

Bits 2:0 – ADSTAT[2:0]

ADC Module Cycle Multi-Stage Status bits(1)
ValueDescription
111 ADC module is in 2nd conversion stage
110 ADC module is in 2nd acquisition stage
101 ADC module is in 2nd precharge stage
100 ADC computation is suspended between 1st and 2nd sample; the computation results are incomplete and awaiting data from the 2nd sample (2,3)
011 ADC module is in 1st conversion stage
010 ADC module is in 1st acquisition stage
001 ADC module is in 1st precharge stage
000 ADC module is not converting
If ADCS = 1, and FOSC < FRC, the indicated status may not be valid. If ADC clock source is ADCRC and FOSC < ADRC, the indicated status may not be valid. STAT = 'b100 appears between the two triggers when DSEN = 1 and CONT = 0.