28.7.2 Endpoint Status - Default Type
This register description is valid for all modes except the Isochronous mode. When
the Endpoint Type (TYPE) bit field in the Endpoint Control (EPn.CTRL)
register is written to ‘ISO’, see Endpoint Status - Isochronous Type for the correct
description.
The Endpoint Status register is modified by the USB hardware.
The application modifies this register using the RMW register interface to
avoid data hazards. See the “Endpoint Registers – Concurrency and
Hazards” section for more details. Flag/status registers in AVR
are usually cleared by writing a ‘1’ and can be set only by
hardware. These status bits in RAM are an exception where you can
write‘0’ to clear them or ‘1’ to set
them.
| Name: | EPn.STATUS |
| Offset: | 0x00 + n*0x08 [n=0..7] |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UNFOVF | TRNCOMPL | EPSETUP | STALLED | BUSNACK | TOGGLE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | x | x | x | x | x | x |
Bit 6 – UNFOVF Underflow / Overflow Endpoint Flag
The UNF flag is set when an input endpoint is not ready to send data to the host
in response to an IN token for input endpoints.
The OVF flag is set when an output endpoint is not ready to accept data
from the host following an OUT token for output
endpoints.
Bit 5 – TRNCOMPL Transaction Complete Flag
This flag is set when an IN or OUT transaction
on the endpoint has successfully completed. When setting this flag,
the USB hardware will also set the Transaction Complete (TRNCOMPL)
flag in the Interrupt Flags B (INTFLAGSB) register - unless the
TRNCOMPL Interrupt Disable (TCDSBL) bit in the Endpoint Control
(EPn.CTRL) register is ‘1’.
For multipacket transfers, TRNCOMPL is not set for each transaction but only when a multipacket transfer has been completed.
Bit 4 – EPSETUP Endpoint SETUP Complete Flag
This flag is set when a SETUP transaction has been completed successfully. When
this flag is set, all IN and OUT
transactions to control endpoints are responded to with a NAK.
This flag must be cleared by the application before decoding the request sent in the setup stage of a control transfer.
Bit 3 – STALLED Endpoint STALL Flag
This flag is set when a STALL handshake has been sent to the host in response to
an IN or OUT transaction.
Bit 1 – BUSNACK Data Buffer Not Acknowledge
This flag is set when a packet has been received. When this bit is set the USB
peripheral will discard incoming data to the data buffer in an
OUT transaction and will not return any data
from the data buffer in an IN transaction. For
control, bulk and interrupt endpoints a NAK handshake is returned.
After processing the packet, this flag must be cleared by the application. This bit can be written by the application to force returning a NAK to the host, e.g., during initialization. The setting of BUSNACK does not affect the ACKing of SETUP packets.
Bit 0 – TOGGLE Data Toggle
This indicates if a DATA0 or DATA1 PID is expected in the next data packet for an output endpoint, and if a DATA0 or DATA1 PID will be sent in the next transaction for an input endpoint. In most cases, TOGGLE is updated by hardware. The Programming Manual describes the exceptional cases where TOGGLE needs to be updated by the application.
| Value | Name | Description |
|---|---|---|
| 0x0 | DATA0 | Data packet DATA0 |
| 0x1 | DATA1 | Data packet DATA1 |