28.4 Register Summary - USBn

OffsetNameBit Pos.76543210
0x00CTRLA7:0ENABLE FIFOENSTFRNUMMAXEP[3:0]
0x01CTRLB7:0    URESUMEGNAUTOGNAKATTACH
0x02BUSSTATE7:0   WTRSMURESUMEDRESUMESUSPENDEDBUSRST
0x03ADDR7:0 ADDR[6:0]
0x04FIFOWP7:0   FIFOWP[4:0]
0x05FIFORP7:0   FIFORP[4:0]
0x06EPPTR7:0EPPTR[7:0]
15:8EPPTR[15:8]
0x07INTCTRLA7:0SOFSUSPENDRESUMERESETSTALLEDUNFOVF 
0x08INTCTRLB7:0  TRNCOMPL   GNDONESETUP
0x09INTFLAGSA7:0SOFSUSPENDRESUMERESETSTALLEDUNFOVF 
0x0AINTFLAGSB7:0  TRNCOMPL  RMWBUSYGNDONESETUP

0x0B

...

0x3F

Reserved         
0x40STATUS[0].OUTCLR7:0RMWSTATUS[7:0]
0x41STATUS[0].OUTSET7:0RMWSTATUS[7:0]
0x42STATUS[0].INCLR7:0RMWSTATUS[7:0]
0x43STATUS[0].INSET7:0RMWSTATUS[7:0]
0x44STATUS[1].OUTCLR7:0RMWSTATUS[7:0]
0x45STATUS[1].OUTSET7:0RMWSTATUS[7:0]
0x46STATUS[1].INCLR7:0RMWSTATUS[7:0]
0x47STATUS[1].INSET7:0RMWSTATUS[7:0]
0x48STATUS[2].OUTCLR7:0RMWSTATUS[7:0]
0x49STATUS[2].OUTSET7:0RMWSTATUS[7:0]
0x4ASTATUS[2].INCLR7:0RMWSTATUS[7:0]
0x4BSTATUS[2].INSET7:0RMWSTATUS[7:0]
0x4CSTATUS[3].OUTCLR7:0RMWSTATUS[7:0]
0x4DSTATUS[3].OUTSET7:0RMWSTATUS[7:0]
0x4ESTATUS[3].INCLR7:0RMWSTATUS[7:0]
0x4FSTATUS[3].INSET7:0RMWSTATUS[7:0]
0x50STATUS[4].OUTCLR7:0RMWSTATUS[7:0]
0x51STATUS[4].OUTSET7:0RMWSTATUS[7:0]
0x52STATUS[4].INCLR7:0RMWSTATUS[7:0]
0x53STATUS[4].INSET7:0RMWSTATUS[7:0]
0x54STATUS[5].OUTCLR7:0RMWSTATUS[7:0]
0x55STATUS[5].OUTSET7:0RMWSTATUS[7:0]
0x56STATUS[5].INCLR7:0RMWSTATUS[7:0]
0x57STATUS[5].INSET7:0RMWSTATUS[7:0]
0x58STATUS[6].OUTCLR7:0RMWSTATUS[7:0]
0x59STATUS[6].OUTSET7:0RMWSTATUS[7:0]
0x5ASTATUS[6].INCLR7:0RMWSTATUS[7:0]
0x5BSTATUS[6].INSET7:0RMWSTATUS[7:0]
0x5CSTATUS[7].OUTCLR7:0RMWSTATUS[7:0]
0x5DSTATUS[7].OUTSET7:0RMWSTATUS[7:0]
0x5ESTATUS[7].INCLR7:0RMWSTATUS[7:0]
0x5FSTATUS[7].INSET7:0RMWSTATUS[7:0]