32.5.10 Control F
| Name: | CTRLF |
| Offset: | 0x09 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FREERUN | LEFTADJ | SAMPNUM[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 5 – FREERUN Free-Running
This bit controls whether the ADC Free-Running mode is enabled or not.
Free-Running mode is not supported in Series mode.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | The ADC Free-Running mode is disabled |
| 0x1 | ENABLE | The ADC Free-Running mode is enabled. The first conversion is started by writing the IMMEDIATE setting to the START bit field in the Command (ADCn.COMMAND) register. In Free-Running mode, a new conversion is started as soon as the previous conversion or accumulation has been completed, which is signaled by RESRDY in the Interrupt Flags (ADCn.INTFLAGS) register. |
Bit 4 – LEFTADJ Left Adjust
This bit controls whether the ADC output is left adjusted or not.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | The ADC output left adjustment is disabled |
| 0x1 | ENABLE | The ADC output left adjustment is enabled |
Bits 2:0 – SAMPNUM[2:0] Sample Accumulation Number Select
This bit field selects the number of consecutive ADC samples accumulated automatically into the ADC Result (ADCn.RESULT) register. The most recent sample will be available in the ADC Sample (ADCn.SAMPLE) register.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No accumulation, single sample per conversion result |
| 0x1 | ACC2 | 2 samples accumulated |
| 0x2 | ACC4 | 4 samples accumulated |
| 0x3 | ACC8 | 8 samples accumulated |
| 0x4 | ACC16 | 16 samples accumulated |
| 0x5 | ACC32 | 32 samples accumulated |
| 0x6 | ACC64 | 64 samples accumulated |
| Other | - | Reserved |