1 Features

  • Arm Cortex-A5 Core
    • ARMv7-A architecture
    • Arm TrustZone®
    • NEON™ Media Processing Engine
    • Up to 500 MHz
    • ETM/ETB 8 Kbytes
  • Memory Architecture
    • Memory Management Unit
    • 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
    • 128-Kbyte L2 cache configurable to be used as an internal SRAM
    • DDR2-SDRAM memory up to 1 Gb
    • LPDDR2-SDRAM memory up to 2 Gb
    • One 128-Kbyte scrambled internal SRAM
    • One 160-Kbyte internal ROM
      • 64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader
      • 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
    • High-bandwidth scramblable 16-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting Winbond DDR2-SDRAM up to 1 Gb, including “on-the-fly” encryption/decryption path
    • High-bandwidth scramblable 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting AP memory LPDDR2-SDRAM up to 2 Gb , including “on-the-fly” encryption/ decryption path
    • 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
  • System Running up to 166 MHz
    • Reset controller, shutdown controller, periodic interval timer, independent watchdog timer and secure Real-Time Clock (RTC) with clock calibration
    • One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for USB high speed
    • Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)
    • Internal low-power 12 MHz RC and 32 KHz typical RC
    • Selectable 32.768-Hz low-power oscillator and 8 to 24 MHz oscillator
    • 51 DMA Channels including two 16-channel 64-bit Central DMA Controllers
    • 64-bit Advanced Interrupt Controller (AIC)
    • 64-bit Secure Advanced Interrupt Controller (SAIC)
    • Three programmable external clock signals
  • Low-Power Modes
    • Ultra-Low-Power mode with fast wake-up capability
    • Low-Power Backup mode with 5-Kbyte SRAM and SleepWalking™ features
      • Wake-up from up to nine wake-up pins, UART reception, analog comparison
      • Fast wake-up capability
      • Extended Backup mode with LPDDR2/DDR2-SDRAM in Self-Refresh mode
  • Peripherals
    • LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit parallel RGB
    • ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface
    • Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier
    • One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)
    • One Pulse Density Modulation Interface Controller (PDMIC)
    • One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host ports (UHPHS)
    • One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface
    • One 10/100 Ethernet MAC (GMAC)
      • Energy efficiency support (IEEE 802.3az standard)
      • Ethernet AVB support with IEEE802.1AS time stamping
      • IEEE®802.1Qav credit-based traffic-shaping hardware support
      • IEEE1588 Precision Time Protocol (PTP)
    • Two high-speed memory card hosts:
      • SDMMC0: SD 3.0, eMMC 4.51, 8 bits
      • SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
    • Two host/client Serial Peripheral Interfaces (SPI)
    • Two Quad Serial Peripheral Interfaces (QSPI)
    • Five FLEXCOMs (USART, SPI and TWI)
    • Five UARTs
    • Two host CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered transmission
      Warning: MCAN implements the non-ISO CAN FD frame format and therefore does not pass the CAN FD Conformance Test according to ISO 16845-1:2016.
    • One Rx only UART in backup area (RXLP)
    • One analog comparator (ACC) in backup area
    • Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS (TWIHS)
    • Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes
    • One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller
    • One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability
  • Safety
    • Zero-power Power-On Reset (POR) cells
    • Main crystal clock failure detector
    • Write-protected registers
    • Integrity Check Monitor (ICM) based on SHA256
    • Memory Management Unit
    • Independent watchdog
  • Security
    • 5 Kbytes of internal scrambled SRAM:
      • 1 Kbyte non-erasable on tamper detection
      • 4 Kbytes erasable on tamper detection
    • 256 bits of scrambled and erasable registers
    • Up to eight tamper pins for static or dynamic intrusion detections(1)
    • Environmental monitors on specific versions: temperature, voltage, frequency and active die shield(2)
    • Secure Boot Loader(3)
    • On-the-fly AES encryption/decryption on LPDDR2/DDR2-SDRAM and QSPI memories (AESB)
    • RTC including time-stamping on security intrusions
    • Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)
  • Hardware Cryptography
    • SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2
    • AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197
    • TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
    • True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs 140-2 and 140-3
  • Up to 128 I/Os
    • Fully programmable through set/clear registers
    • Multiplexing of up to eight peripheral functions per I/O line
    • Each I/O line can be assigned to a peripheral or used as a general purpose I/O
    • PIO controller features a synchronous output providing up to 32 bits of data output in one write operation
  • Operating Conditions
    • Ambient temperature: -40°C to +85°C
Note:

  1. For information specific to dynamic tamper protection (PIOBU), refer to the document SAMA5D2 External Tamper Protections (document no. 44095). Contact a Microchip sales representative for details.

  2. For environmental monitors, refer to the document SAMA5D23 and SAMA5D28 Environmental Monitors (document no. 44036), available under Non-Disclosure Agreement (NDA). Contact a Microchip sales representative for details.
  3. For secure boot strategies, refer to the document SAMA5D2 Series Secure Boot Strategy (document no. DS00002435), available under Non-Disclosure Agreement (NDA). Contact a Microchip sales representative for details.