3 LPDDR2-SDRAM Features

  • Power Supply: DDRM_VDD18 = 1.7 to 1.9V
  • Power Supply: DDRM_VDD12 = 1.14 to 1.3V
  • Double Data Rate Architecture: Two Data Transfers per Clock Cycle
  • Burst Length (BL): 8
  • Write Latency (WL): 1
  • Read Latency (RL): 3
  • Bi-Directional, Differential Data Strobes (DQS and DQSN) are Transmitted/Received with Data
  • Edge-Aligned with Read Data and Center-Aligned with Write Data
  • Differential Clock Inputs (CLK and CLKN)
  • Data Masks (DM) for Write Data
  • Commands Entered on each Positive CLK Edge, Data and Data Mask are Referenced to Both Edges of DQS
  • Interface: HSUL_12
  • Auto-Refresh and Self-Refresh Modes
  • Low Power Consumption
  • JEDEC LPDDR2-S4B Compliance
  • Partial Array Self-Refresh (PASR)
  • Auto Temperature Compensated Self-Refresh (ATCSR) by Built-in Temperature Sensor
  • Deep Power-Down Mode