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2 DDR2-SDRAM Features
- Power Supply: DDRM_VDD, DDRM_VDDL, DDRM_VDDQ = 1.8 V ±0.1
V
- Double Data Rate Architecture: Two Data Transfers per Clock
Cycle
- CAS Latency: 3
- Burst Length: 8
- Bi-Directional, Differential Data Strobes (DQS and DQSN) are
Transmitted/Received with Data
- Edge-Aligned with Read Data and Center-Aligned with Write
Data
- DLL Aligns DQ and DQS Transitions with Clock
- Differential Clock Inputs (CLK and CLKN)
- Data Masks (DM) for Write Data
- Commands Entered on Each Positive CLK Edge, Data and Data
Mask are Referenced to Both Edges of DQS
- Auto-Refresh and Self-Refresh Modes
- Precharged Power-Down and Active Power-Down
- Write Data Mask
- Write Latency = Read Latency - 1 (WL = RL - 1)
- Interface: SSTL_18