12.10.17 PIR7
Note: Interrupt flag bits are set when an
Interrupt condition occurs, regardless of the state of its corresponding enable bit or
the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag
bits are cleared before enabling an interrupt.
| Name: | PIR7 |
| Offset: | 0x0093 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OPA1CIF | |||||||||
| Access | R/W/HS | ||||||||
| Reset | 0 |
Bit 0 – OPA1CIF OPA1 Self-Calibration Complete Interrupt Flag
| Value | Description |
|---|---|
| 1 | OPA1 Self-Calibration has completed (must be cleared in software) |
| 0 | OPA1 Self-Calibration event has not occurred |