✝ Data found in the “Typ.” column is at TA = 25°C
and VDD = 3.0V unless otherwise specified. These
parameters are for design guidance only and are not tested.
Note:
- The main
clock frequency (CLK_MAIN) is configured by the Clock Select
(CLKSEL) bit field, as described in the CLKCTRL - Clock
Controller section.
- The main
clock frequency (CLK_MAIN) must meet the voltage
requirements defined in Standard Operating
Conditions.
- The
Instruction Cycle Period (TCY) is identical to
the input oscillator time base period. Exceeding these
limits may result in incorrect code execution and/or
higher-than-expected current consumption. All devices are
tested to operate at ‘min’ values with an external clock
applied to the EXTCLK pin. When using an external clock
input, the ‘max’ cycle time limit is ‘DC’ (no clock) for all
devices.
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